The present invention broadly relates to output buffers used to reduce current and voltage spikes produced by Integrated circuits such as MOSFETS, and deals more particularly with a digital output buffer for controlling the slew rate on an output signal while reducing crowbar current.
Output buffers are used in digital integrated circuits to drive an external load. Typically, the size of a load is not always known in advance, consequently most output buffers are designed to provide enough current to drive loads up to a maximum permissible level. This is normally accomplished by providing an output transistor that is sufficiently enlarge to drive a maximum permissible load, or by providing a number of smaller transistors coupled in parallel to drive the maximum permissible load.
Continuing advancements in the integrated circuit technologies has lead to improvements in the speed of integrated circuits, i.e. the time in which the output of a circuit reacts in response to a new input. Increasing integrated circuit speed has resulted in faster rise and fall times of the output voltage. Similarly, the fast rise and fall times of the output voltages have resulted in abrupt transitions in output current. In the case of output buffers used with power transistors, a problem is encountered when the output buffers are quickly turned on or off. Because the current flow is so large, fast switching of prior art buffers can produce transient such as noise spikes on the power, ground and data busses which result in data errors, latch-up and other problems in a digital electronic circuitry,
One solution to this problem involves a technique referred to as slew-rate control. Slew-rate is defined as the rate of output transition of the buffer in volts per unit-time. Conventional digital buffers with slew-rate control use a number of parallel transistors which can be sequentially turned on to reduce the abruptness of the transition and thereby reduce the above mentioned transients. A plurality of transistors forming the buffer can be controlled by delay elements or by feed-back from the output of the buffer.
The transistor of a digital output buffer can be arranged as a pull-up network which can pull up the output of a buffer to a certain level, and a pull-down network which can pull down the output of the buffer to a different, lower voltage. Because of the time delay involved in sequential turn on the transistors of each network, a problem is sometime encountered with slew-rate control when one of the networks of the buffer is being slowly turned on while the other network of the buffer is being slowly turned off. The problem resides in the fact that for a brief period of time, both networks are on. In other words, the network being turned on becomes active before the network being turned off completes it""s turn-off sequence. As a result, during the period that both networks are active, a very large current know as a xe2x80x9ccrowbarxe2x80x9d is allowed to flow.
Although a number of solutions to this problem have been proposed, none has been effective in achieving slow turn-on of the transistors in each network with the ability to quickly achieve turn-off so as to reduce or eliminate crow bar current. The present invention is directed towards satisfying this need in the art.
According to the invention, a digital output buffer is provided with use in an integrated circuit for driving an external load. The buffer includes a pull-up network for pulling up the voltage at the buffer output and a pull-down network for pulling down the voltage at the output. Each of the networks includes a plurality of switchable conducting devices, such as transistors, for controlling the flow of current from the buffer input to the buffer output, as well as a plurality of controllable delay devices for producing delayed, sequential switching of the conducting devices so as to control the slew rate of a signal propagating from the buffer input to the buffer output. Each of the delay devices preferably includes an unbalanced pair of passgates formed of complementary NMOS and PMOS transistors. One of the passgate transistors possesses a relatively high resistance, while the other transistor possesses a low relatively low resistance. During turn on of a network, the passgate transistors having the high resistance control the conducting devices so as to achieve a desired slew-rate. However, the passgate transistors having a low resistance are responsive to a turn-off signal to quickly turn off all of the conducting devices, without delay.
Accordingly, it is a primary object of the present invention to provide an output buffer for an integrated circuit, such a MOSFET that provides improved slew-rate control while minimizing or eliminating crowbar current.
Another object of the invention is to provide an output buffer as described above which may be constructed using conventional, existing circuit components.
A further object of the invention is to provide an improved output buffer as described above that effectively achieves slew-rate control through the provision of a variable resistance that forms part of an RC circuit that determines the slew rate.
A still further object of the invention is to provide an output buffer as described above which achieves turn on and turn off of separate transistor networks forming the buffer, without the need for additional logic circuitry.
These and further objects and advantages invention will be made clear or become apparent during the course of the following description of a preferred embodiment of the invention.